MATLAB-Based Modeling and Spectral Analysis of Inter-Channel Mismatch Errors in Time-Interleaved ADCs

Authors

  • Zhendong Wang School of Navigation and Shipping, Shandong Jiaotong University, Weihai 264200, China

DOI:

https://doi.org/10.54691/9mw1h965

Keywords:

Time-interleaved analog-to-digital converter; inter-channel mismatch; MATLAB modeling; gain mismatch; offset mismatch; timing skew; spectral analysis.

Abstract

Time-interleaved analog-to-digital converters (TIADCs) increase the overall sampling rate by operating multiple sub-ADCs with uniformly shifted sampling phases. However, channel-to-channel differences caused by device variations, analog front-end mismatch, and sampling-clock errors introduce deterministic interleaving spurs that degrade the output spectrum. This paper develops a MATLAB-based numerical model for the three dominant mismatch mechanisms: gain mismatch, offset mismatch, and timing-skew mismatch. A four-channel, 14-bit, 1-GS/s TIADC with 8192 samples is considered. The ideal interleaved sampling sequence is first formulated, after which the three mismatch terms are incorporated into a unified channel-dependent output model. FFT-based analysis is then used to identify the spectral characteristics of each mismatch type. Gain mismatch produces input-frequency-dependent image spurs, offset mismatch generates fixed components associated with the interleaving frequency, and timing skew produces input-dependent images whose amplitudes increase with the input-signal slope. The resulting model provides a controllable simulation platform for analyzing TIADC nonidealities and for supporting subsequent mismatch-estimation and digital-calibration studies.

Downloads

Download data is not yet available.

References

[1] Black, W. C., & Hodges, D. A. (1980). Time interleaved converter arrays. IEEE Journal of Solid-State Circuits, 15(6), 1022–1029. https://doi.org/10.1109/JSSC.1980.1051512.

[2] Razavi, B. (2013). Design considerations for interleaved ADCs. IEEE Journal of Solid-State Circuits, 48(8), 1806–1817. https://doi.org/10.1109/JSSC.2013.2258814

[3] Dyer, K. C., Fu, D., Lewis, S. H., et al. (1998). An analog background calibration technique for time-interleaved analog-to-digital converters. IEEE Journal of Solid-State Circuits, 33(12), 1912–1919. https://doi.org/10.1109/4.735531

[4] Fu, D., Dyer, K. C., Lewis, S. H., et al. (1998). A digital background calibration technique for time-interleaved analog-to-digital converters. IEEE Journal of Solid-State Circuits, 33(12), 1904–1911. https://doi.org/10.1109/4.735530

[5] Jamal, S. M., Fu, D., Chang, N. C. J., et al. (2002). A 10-b 120-Msample/s time-interleaved analog-to-digital converter with digital background calibration. IEEE Journal of Solid-State Circuits, 37(12), 1618–1627. https://doi.org/10.1109/JSSC.2002.804327

[6] Xiong, W., Zhang, Z., Lang, L., et al. (2023). A novel fully digital feedforward background calibration technique for timing mismatch in M-channel time-interleaved ADCs. Electronics, 12(9), 1965. https://doi.org/10.3390/electronics12091965

Downloads

Published

22-09-2026

Issue

Section

Articles